The present invention relates generally to digital-to-analog (D/A) conversion for converting a digital input signal to an analog output signal, and more particularly, to a D/A converting method and a D/A converter which are capable of facilitating reduction or removal of relative errors among weight generating elements, which are introduced in the course of manufacturing of converters.
Conventionally, as a general conversion scheme for implementing D/A conversion, a so-called multi-bit scheme is known. Referring to FIG. 22, the D/A conversion in accordance with the multi-bit scheme will be described below. For a binary digital signal to be converted to an analog signal, a converting element or a weight generating element is provided for each of digits which constitutes the signal. The respective weight generating elements are designed and manufactured such that their weights have preset values for associated bits. In an example shown in FIG. 22, four binary bits (=16 levels) are expressed by four different forms of weight, i.e., x1, x2, x4, x8 weights. In the D/A conversion in accordance with this scheme, the weight generating elements are controlled ON/OFF in accordance with the binary states of the respective digits of the binary digital signal (a black circle represents ON state, and a white circle represents OFF state) to generate an analog signal represented by the binary digital signal. With the use of this scheme, the total number of the weight generating elements is equal to the number of digits of a binary digital signal or a digital code if the simplest configuration is employed. Thus, a digital-to-analog (D/A) converter of the type mentioned above can be implemented on a relatively small chip area since a required number of elements is small, although respective elements may differ in physical size.
FIG. 23 shows another conventional conversion scheme for D/A conversion which comprises unit weight generating elements such as current sources having an almost equal weight to each other, equal in number to the decimal number represented by a binary digital code. Laid-open Japanese Patent Application No. 204527/89 discloses an example of a digital-to-analog converter in accordance with the configuration as shown. In the example shown in FIG. 23, binary four bits (=16 levels) are expressed by 16 single-weight generating elements, i.e., elements having a form of weight of x1. This type of D/A converter turns on a number of weight generating elements equal to a decimal value represented by a digital code, and sums up analog outputs generated thereby to derive a final analog signal. While the individual unit weight generating elements are less likely to generate errors in their outputs as compared with the first scheme mentioned above, the unit weight generating elements generally have minor errors which may cause nonlinearity appearing in the level of a resulting analog output signal, an increased distortion in an AC output signal, and so on, thereby limiting the analog performance. A technique for solving these troubles has been proposed. Specifically, in a time period in which a given digital code is converted to an analog amount, i.e., in a main period, a combination of used weight generating elements is dynamically changed to average output errors among unit weight generating elements. For combining unit weight generating elements, a variety of methods have been proposed. For example, Laid-open Japanese Patent Applications Nos. 48827/82 and 204527/89 disclose such methods. In either of the methods, however, a multiplicity of unit conversion elements are selected and used to produce a whole analog output level. The total number of unit conversion elements required by such a method for a 4-bit converter, by way of example, amounts to at least 15 (=24xe2x88x921). For a 16-bit converter typically employed in the field of PCM audio, however, the number of required unit conversion elements will rise up to as much as 65,535 (=216xe2x88x921). It will be understood that a D/A converter, if configured in accordance with the foregoing scheme, would require a much larger chip area than that required by the first scheme.
FIGS. 24 and 25 show tables each representing the relationship between respective levels and weight generating elements for expressing the levels in a sign-magnitude format. More specifically, FIG. 24 shows a table relating each level to weight generating elements when the conventional multi-bit scheme in FIG. 22 is used in the sign-magnitude format. As shown, two D/A converters for implementing the conversion in FIG. 22 (each having two weight generating elements for each of x1, x2, x4, x8 weights), and an additional x1 weight generating element for expressing a sign bit are provided. FIG. 25 in turn shows a table relating each level to unit weight generating elements when the conventional conversion scheme of FIG. 23 is used in the sign-magnitude format, wherein two D/A converters for implementing the conversion of FIG. 23 (each having 15 unit weight generating elements), and an additional unit weight generating element for expressing a sign bit (xcex1) are provided.
The prior art schemes described above imply the following shortcomings. Specifically, in the multi-bit scheme or the first conversion scheme, a relative linearity among all weighted conversion elements must be maintained in accordance with a resolution required for a D/A converter. To meet this requirement, a technique called xe2x80x9ctrimmingxe2x80x9d has been conventionally used for each of manufactured converters to make adjustments among conversion elements in order to enhance a relative manufacturing accuracy. This technique is extremely expensive for implementing a highly accurate D/A converter.
In the second conversion scheme, on the other hand, the total number of required unit converting elements (weight generating elements) exponentially increases and become immense, as a larger number of digital bits or a more accurate converter is implemented, as has been described in the aforementioned example. This means that a large chip area is required when a D/A converter is implemented in a semiconductor integrated circuit. Furthermore, large variations and so on in a variety of parameters in such a large chip area would increase the cost of a highly accurate D/A converter.
It is therefore an object of the present invention to provide a method and apparatus which are capable of realizing a digital-to-analog converter having a required accuracy in a smaller chip area.
It is another object of the present invention to provide a method and apparatus which are capable of implementing a required digital-to-analog converter at a lower cost.
It is a further object of the present invention to provide a highly accurate digital-to-analog converter at a lower price.
To achieve the above objects, the present invention provides, in a first aspect, a digital-to-analog converting method for converting a digital signal input comprising a first plural number of bits each having a different weight from a digital form to an analog form. The digital-to-analog converting method comprises the steps of (A) dividing the first number of bits into a second plural number of bit groups, and using one form of weight for each of the bit groups to convert each bit group into an analog form to generate the second number of bit group analog outputs; and (B) forming an analog signal output representative of the digital signal input from the second number of bit group analog outputs.
Also, in the present invention, the same type of digital-to-analog converting scheme may be used for the bit groups. In addition, the first number of bits may or may not include a sign bit.
Further, in the present invention, the step (A) may include the steps of (a) dividing the first number of bits into the second number of bit groups; (b) selecting the one form of weight for use in expressing each bit group of the second number of bit groups; (c) determining a number of weights having said selected form of weight required to express each of the bit groups with the selected form of weight; and (d) using said selected form of weight and the determined number of weights having said selected form of weight to convert said each bit group to said bit group analog outputs. Further, the step (d) may include the steps of (e) determining a third maximum number of weights having the selected form of weight required to express each bit group with the selected form of weight; (f) providing the second number of weight generator groups for the plurality of bit groups by providing a weight generator group comprising the third number of weight generators having a weight corresponding to the selected form of weight for each bit group; and (g) controlling the second number of weight generator groups in response to the second number of bit groups to generate the bit group analog outputs.
Further, in the present invention, as the selected form of weight for use in expressing each bit group in the plurality of bit groups, it is possible to select a weight associated with the least significant bit of each bit group corresponding thereto, or a weight associated with a bit in the first number of bits located at a bit position lower than the least significant bit. In addition, the second number may be equal to or more than two and smaller than the first number.
Further, in the present invention, the third number may be equal to a fourth number which is a minimum number of weights having the selected form of weight required for expressing each bit group with said selected form of weight. Alternatively, the third number may be the sum of a fourth number which is a minimum number of weights having the selected form of weight required for expressing each bit group therewith, and a fifth number used for correcting errors between weight generators in the second number of weight generator groups.
In the case mentioned above, the fifth number may have a value specific to each weight generator group. Then, the step of (g) may include the steps of (h) preparing a sixth plural number of different combination patterns of status signals, representing the status each of all weight generators included in the second number of weight generator group, for use in an analog expression for each of values represented by the digital signal input, wherein the status signal has a first state for causing an associated weight generator to generate a weighted analog output having a weight of the weight generator, and a second state for causing the associated weight generator to generate a weighted analog output without the weight; (i) selecting status signals from the sixth number of different status signal combination patterns within a first period in which a given digital signal input is converted to an analog signal output; (j) controlling the all weight generators using the selected status signals to generate the weighted analog outputs from the all weight generators; and (k) adding the weighted analog outputs generated from the all weight generators to generate an analog signal output corresponding to the given digital signal input. Further, the step (i) may selectively use all of the sixth number of different combination patterns of status signals at least once within the first period. Alternatively, the step of (i) may selectively use all of the sixth number of different combination patterns of status signals at least once within a sequence of a plurality of the first periods, and selectively use a portion of the sixth number of different combination patterns of status signals within each first period of the sequence of the plurality of the first periods. Also, in the present invention, the digital-to-analog converting method may further include the step of canceling a constant offset in the magnitude of the analog signal output. In this event, the constant offset may include only a constant difference from an analog value represented by the digital signal input in the value of the analog signal output.
Also, according to the present invention, the plurality of different weight generators may comprise voltage or current sources each having a weight corresponding to the weight of each of the weight generators. The plurality of different weight generators may comprise voltage or current sources having a weight of a common magnitude, and weighting means for applying each source with a weight of each weight generator. The weighting means may comprise an R-2R ladder circuit.
According to a second aspect, the present invention provides a digital-to-analog converter for converting a digital signal input comprising a first plural number of bits, each having a different weight, from a digital form to an analog form. The digital-to-analog converter comprises decoding means connected to receive a digital signal input for dividing the first number of bits into a second plural number of bit groups; a second number of converting means provided for the second number of bit groups, wherein each of the bit group converting means selectively uses a form of weight for each bit group associated therewith, thereby converting the bit group to the analog form in response to the second number of bit groups to generate the second number of bit group analog outputs; and adding means for adding the second number of bit group analog outputs to form an analog signal output representative of the digital signal input.
In the present invention, the same type of digital-to-analog converting method may be used for the bit groups. The first number of bits may or may not include a sign bit.
Also, in the present invention, each of the bit group converting means may include a weight generator group having a third number of weight generators having a weight corresponding to the selected form of weight for each bit group, wherein the third number is a maximum number of weights having the selected form of weight required to express each bit group therewith. Also, as the selected form of weight for use in expressing each bit group in the plurality of bit groups, a weight associated with the least significant bit of each bit group corresponding thereto, or a weight associated with a bit in the first number of bits located at a bit position lower than the least significant bit is selected.
Further, in the present invention, the second number may be equal to or more than two and smaller than the first number. The third number in turn may be equal to a fourth number which is a minimum number of weights having the selected form of weight required for expressing each bit group therewith.
Alternatively, the third number may be the sum of a fourth number which is a minimum number of weights having the selected form of weight required for expressing each bit group therewith, and a fifth number used for correcting errors between weight generators in the second number of weight generator groups. In this case, the fifth number may have a value specific to each weight generator group.
Also, in the present invention, the decoding means may include pattern generating means for generating a sixth plural number of different combination patterns of status signals representing the status of all weight generators included in the second number of weight generator groups, for use in an analog expression for each of values represented by the digital signal input, wherein the status signal has a first state for causing an associated weight generator to generate a weighted analog output having a weight of the weight generator, and a second state for causing the associated weight generator to generate a weighted analog output without the weight; and status signal selecting means for selecting status signals from the sixth number of different status signal combination patterns within a first period in which a given digital signal input is converted to an analog signal output, wherein the status signal selecting means uses the selected status signals to control the all weight generators to generate the weighted analog outputs from the all weight generators.
Further, in the present invention, the status signal selecting means may select and use the status signals of all of the sixth number of different combination patterns at least once within the first period. Alternatively, the status signal selecting means may select and use the status signals of all of the sixth number of different combination patterns of status signals at least once within a sequence of a plurality of the first periods, and select and use a portion of the sixth number of different combination patterns of status signals within each first period of the sequence of the plurality of the first periods.
Further, in the present invention, the digital-to-analog converter may include canceling means for canceling a constant offset in the magnitude of the analog signal output. The constant offset may be only a constant difference from an analog value represented by the digital signal input in the value of the analog signal output. Also, the plurality of different weight generators may comprise voltage or current sources each having a weight corresponding to the weight of each weight generator. The plurality of different weight generators may comprise voltage or current sources having a weight of a common magnitude, and weighting means for applying each source with a weight of each weight generator. The weighting means may comprise an R-2R ladder circuit.
Further, according to a third aspect, the present invention provides a sign-magnitude type digital-to-analog converter for converting a digital signal input from a digital form to an analog form, where the digital signal input is comprised of a sign bit representative of a sign, and a first plural number of bits each representative of a magnitude and having a different weight from each other. The digital-to-analog converter comprises decoding means connected to receive a digital signal input for dividing the first number of bits into a second plural number of bit groups; a second plural number of positive bit group converting means provided for the second number of bit groups for use when the sign bit indicates positive, wherein each positive bit group converting means selects and uses a form of weight for each bit group associated therewith, thereby converting the second number of bit groups to the analog form in response to the second number of bit groups to generate the second number of positive bit group analog outputs; a second number of negative bit group converting means provided for the second number of bit groups for use when the sign bit does not indicate positive, wherein each negative bit group converting means selects and uses a form of weight for each bit group associated therewith, thereby converting the second number of bit groups to the analog form in response to the second number of bit groups to generate the second number of negative bit group analog outputs; and adding means for adding the second number of positive bit group analog outputs and the second number of negative bit group analog outputs to form an analog signal output representative of the digital signal input.
Also, in the present invention, the digital-to-analog converter may further include sign bit converting means provided for the sign bit for selecting and using a weight for the sign bit to convert the sign bit to the analog form in response to the sign bit, thereby generating a sign bit analog output, wherein the adding means adds the sign bit analog output to the second number of positive bit group analog outputs and the second number of negative bit group analog outputs to form the analog signal output.
In the present invention, each of the bit group converting means may include a weight generator group having a third number of weight generators having a weight corresponding to the selected form of weight for each bit group, wherein the third number is a maximum number of weights having the selected form of weight required to express each bit group with said selected form of weight.
Also, in the present invention, as the selected form of weight for use in expressing each bit group in the plurality of bit groups, a weight associated with the least significant bit of each bit group corresponding thereto, or a weight associated with a bit in the first number of bits located at a bit position lower than the least significant bit is selected.
Particularly, in the present invention, the second number may be equal to or more than two and smaller than the first number. The third number in turn may be equal to a fourth number which is a minimum number of weights having the selected form of weight required for expressing each bit group therewith. Alternatively, the third number may be the sum of a fourth number which is a minimum number of weights having the selected form of weight required for expressing each bit group therewith, and a fifth number used for correcting errors between weight generators in the second number of weight generator groups. In this case, the fifth number may have a value specific to each weight generator group.
In the present invention, the second number may have the same value for the positive bit group converting means and the negative bit group converting means, or have a different value in between the second number for the positive bit group converting means and the negative bit group converting means.
In the present invention, the decoding means may include pattern generating means for generating a sixth plural number of different combination patterns of status signals representing the status of all of the weight generators, for use in an analog expression for each of values represented by the digital signal input, wherein the status signal has a first state for causing an associated weight generator to generate a weighted analog output having a weight of the weight generator, and a second state for causing the associated weight generator to generate a weighted analog output without the weight; and status signal selecting means for selecting status signals from the sixth number of different status signal combination patterns within a first period in which a given digital signal input is converted to an analog signal output, wherein the status signal selecting means uses the selected status signals to control the all weight generators to generate the weighted analog outputs from the all weight generators.
Also, the decoding means may include, for each of the second number of positive weight generator groups and the second number of negative weight generator groups, pattern generating means for generating a sixth plural number of different combination patterns of status signals representing the status of the second number of weight generators, for use in an analog expression for each of values represented by the digital signal input, wherein the status signal has a first state for causing an associated weight generator to generate a weighted analog output having a weight of the weight generator, and a second state for causing the associated weight generator to generate a weighted analog output without the weight; and status signal selecting means for selecting status signals from the sixth number of different status signal combination patterns within a first period in which a given digital signal input is converted to an analog signal output, wherein the status signal selecting means uses the selected status signals to control the all weight generators to generate the weighted analog outputs from the all weight generators.
Also, in the present invention, the status signal selecting means may select and use the status signals of all of the six number of different combination patterns at least once within the first period. Alternatively, the status signal selecting means may select and use the status signals of all of the six number of different combination patterns at least once within a sequence of a plurality of the first periods, and select and use a portion of the six number of different combination patterns within each first period of the sequence of a plurality of the first periods.
In the present invention, the digital-to-analog converter may further include canceling means for canceling a constant offset in the magnitude of the analog signal output. The constant offset may include only a constant difference from an analog value represented by the digital signal input in the value of the analog signal output. The plurality of different weight generators may comprise voltage or current sources each having a weight corresponding to the weight of each weight generator. The plurality of different weight generators may comprise voltage or current sources having a weight of a common magnitude, and weighting means for applying each source with a weight of each weight generator.
The above and other objects, features and advantages of the present invention will become apparent from the following detailed description of the preferred embodiments when read in conjunction with the accompanying drawings.